Front End RTL Design Automation Engineer

• Well versed in Verilog and SV with good understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and/or gate level verification domain is a must.

• Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process.

• Knowledge on low power design and verification methods using UPF is a must.

• Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend.

• An expert user of one or more of the following verification tools: NC-Sim*, Modelsim*, VCS, Specman*, Debussyand/or Verdi

• Good automation skills in PERL and/or TCL and/or Shell*. Good communication skills (written and verbal).

Qualification: Bachelor/Master s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics

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