Frontend Designer

Job highlights

• 8-15 years experience in SoC design with expertise in RTL coding (Verilog/SystemVerilog), chip-level verification, and MCU ARM core products
• Lead chip-level architecture, RTL design, verification planning, team management, and cross-disciplinary collaboration

Hi

We are hiring for IC Front-End Lead

Job Title: IC Front-End Lead
Work Location: Bangalore
Experience: 8-15 years of exp

Job Description:

We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.

This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.

* Target products are not FPGA-based.*

* Experience with MCU products featuring ARM cores is preferred. *

• Chip Level Verification

• Chip-Level Use Case Understanding

• Verification Plan Formulation, Management, and Review

• Extraction of verification items and formulation of verification program stimulus specifications

• Building Dynamic & Static Verification Environments

• Gate-Level Simulation with Back-Annotated Delays

• Management

• Leadership Experience, Project Planning, Collaboration with Backend and Analog Team

• DFE Team Management

• Documentation

• Continuous Improvement Suggestions

• Functional Safety Standards

• RTL Design & Quality Verification

• RTL Quality Control

• RTL Coding Skills (Verilog HDL/System Verilog)

• RTL Quality Check Execution; EDA Tools for RTL Quality Checks

• Architecture Design

• Chip-Level System Architecture Design

• Block-level microarchitecture design

• Constraint Creation and Synthesis (SDC/STA)

• Timing and synthesis constraints

• Synthesis trial and STA report confirmation

• Chip Level Assembly

• Chip-Level Assembly Using EDA Tools

• Power System Design

• Multi-Power Domain Design

• Power System Model Design

• Testing, On-Board Evaluation, and Mass Production Support

• Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)

• Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)

• Power Estimate

• Power Analysis Using EDA Tools and Design Feedback

• Power Estimation During Feasibility Stage

Regards,

Sri Lakshmi