GLS -Gate-Level Simulation Engineer

Job highlights

• Qualifications: . Bachelors or Masters degree in Electrical Engineering,Computer Engineering,or a related field
• The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS) . Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role

Number of Open Positions: 4

Job Description:

• We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team
• The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS)
• Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role

Key Responsibilities:

• Collaborate with cross-functional teams to define and execute gate-level simulation test plans.
• Develop and implement gate-level simulation strategies for complex digital designs.
• Conduct gate-level simulations to verify the functionality and performance of digital designs.
• Work closely with design and verification teams to identify and resolve issues at the gate level.
• Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process.
• Ensure compliance with industry standards and best practices in gate-level simulation.

Qualifications:

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in gate-level simulation.
• Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Prior experience in gate-level simulation is essential.
• Familiarity with gate-level simulation tools and methodologies.
• Excellent problem-solving skills and attention to detail.
• Effective communication and collaboration skills.
• Ability to work in a dynamic and fast-paced environment