GLS Verification Engineer

Job highlights

• Experience with emulation or acceleration platforms . Disclaimer : This job posting has been aggregated from external source
• Experience: 3-6Yrs in GLS verification .
• . 3 6 years of experience in Design Verification (DV) with exposure to GLS . Strong understanding of digital design fundamentals and timing concepts . .

Job Title: GLS Verification Engineer - 3-6Yrs

Experience: 3-6Yrs in GLS verification

Location: Bangalore

We are looking for a skilled GLS Verification Engineer to validate post-synthesis and post-layout designs through gate-level simulations. The candidate will ensure functional correctness, timing integrity, and robustness of designs under real silicon conditions.

Key Responsibilities:

• Plan and execute Gate-Level Simulations (GLS) for post-synthesis and post-layout netlists

• Perform timing-aware simulations using SDF (Standard Delay Format) back-annotation

• Validate design functionality under setup/hold timing conditions and different PVT corners

• Debug issues related to X-propagation, reset initialization, and clock-domain interactions

• Develop and adapt testbenches (SystemVerilog/UVM) for GLS environments

• Analyze waveform/debug logs to identify root causes of failures

• Collaborate with design, synthesis, and STA teams to resolve timing and functional issues

• Run regression suites and ensure stability of GLS environments

• Ensure coverage completeness and sign-off quality

  Required Skills:

• 3 6 years of experience in Design Verification (DV) with exposure to GLS

• Strong understanding of digital design fundamentals and timing concepts

• Experience with SDF back-annotation and timing simulations

• Knowledge of setup/hold checks, metastability, and clock-domain crossing (CDC)

• Proficiency in SystemVerilog (UVM is a plus)

• Strong debugging skills using simulators (VCS, Questa, Xcelium)

• Experience in handling large netlists and long simulation runtimes

  Preferred Qualifications:

• Experience with low-power GLS and UPF-based simulations

• Familiarity with Static Timing Analysis (STA) concepts

• Exposure to DFT (Design for Test) verification (scan, MBIST, LBIST)

• Scripting skills (Python/Perl/Shell) for automation and regression

• Experience with emulation or acceleration platforms

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.