GPU Design Verification Lead

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams.
• Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems.
• Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration.
• Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure.
• Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure.
• Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features.
• Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes.
• Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams.
• Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers.
• Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization.
• Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders.
• Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.

Main Requirements and Qualifications

• MS or PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related field; equivalent practical experience will also be considered.
• 10+ years of ASIC/SoC design verification experience, including substantial ownership of complex IP, subsystem, or full-chip verification.
• Demonstrated technical leadership experience, including leading verification planning, execution, reviews, debugging, and closure across multiple engineers or teams.
• Strong hands-on expertise in SystemVerilog and UVM, including testbench architecture, constrained-random verification, scoreboarding, assertions, and reusable verification components.
• Proven experience developing verification plans, functional coverage models, coverage-driven verification strategies, and coverage closure.
• Experience with HW/SW co-simulation, firmware-driven verification, regression infrastructure, automation, and scripting using Python, Perl, Tcl, shell, or similar languages.
• Strong debugging, root-cause analysis, and problem-solving skills across RTL, verification environments, software/firmware, and system-level interactions.
• Solid understanding of computer architecture and GPU architecture, including graphics and/or compute pipelines, memory subsystems, cache/coherency, scheduling, and performance behavior.
• Strong written and verbal communication skills, with the ability to communicate technical issues, risks, and recommendations to both engineering and leadership audiences.
• Ability to thrive in a dynamic, fast-paced development environment and collaborate effectively with multi-site, cross-functional teams.
• Preferred Qualifications
• Deep knowledge of GPU shader subsystems, shader execution models, SIMT/SIMD architectures, GPU scheduling, and graphics/compute workloads.
• Experience verifying modern GPU features such as graphics APIs, compute APIs, virtualization, memory protection, power management, coherency, or multi-core GPU scaling.
• Experience with performance verification, emulation, FPGA prototyping, or post-silicon validation.
• Experience applying AI-assisted verification, intelligent regression triage, coverage analysis, test generation, or other verification productivity tools.
• Prior experience building, scaling, or modernizing verification methodologies and infrastructure for large, complex SoC programs.