Hardware Engineer (RTL)

As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal’s thermodynamic hardware

This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely physical design to make sure the design meets area and timing constraints

Because Normal’s chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company

You will be shaping architecture, not just implementing it

This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design

The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel

RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces

Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures

Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage

Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT

Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation

Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed

Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront

Experience in closing coverage to a high level

Ability to work directly with architects and physical designers without needing a large intermediary layer

Strong debugging instincts across simulation, waveforms, and formal counterexamples

Industry experience in ASIC or SoC design

Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route

At least one tapeout in your background, from any node and any company size

Experience at an AI chip company where design and verification were tightly coupled

Familiarity with RISC-V or other open ISAs

Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6

Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Experience with AI-assisted RTL or EDA tooling in your design workflow