Hardware Software Co-design Engineer

Hardware/Software Co-Design Engineer | Memory Architecture / GEM5 / OS Layer

A global leader in telecommunications and technology is seeking a specialized Engineer for a contract role running up to 30th July 2027. This position focuses on HW/SW Codesign for Memory Management Optimization and offers the opportunity to work at the cutting edge of computer architecture and publication-grade research.

The Role

The successful engineer will focus on simulating and optimizing memory architectures for high-performance computing. Responsibilities include simulating many-core models with a focus on memory management using the GEM5 simulator, as well as prototyping and evaluating the impact of memory atomic operations in distributed shared memories. On the software side, the role involves developing the OS layer to enable seamless inter-process communication within the memory model, alongside running experiments, plotting data, and analyzing results for potential industry publications.

Technical Requirements

• Proven hands-on experience utilizing the GEM5 simulator .
• Deep, fundamental knowledge of memory architectures and how they are managed by the OS.
• A detailed, expert-level understanding of memory coherence .
• High proficiency in C or C++ programming.

If you have the required expertise in GEM5 and low-level memory architectures, please apply or reach out directly for more details.

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