Hardware Verification Engineer

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Position Overview

We are looking for a Design Verification Engineer to join our team in Cairo, Egypt.

Area of Responsibility

• Develop and execute verification plans, including testbench architecture and test case development.
• Design and develop co-emulation-based and/or simulation-based verification environments.
• Work with existing complex testbenches targeting different platforms (simulation/co-emulation).
• Integrate software and hardware DUTs and work with different programming languages within the verification environment.
• Implement and monitor code coverage and/or functional coverage metrics to assess verification completeness.
• Run and debug complete testbenches composed of embedded software and hardware components on Questa and/or Veloce platforms.
• Work closely with design and architecture teams to understand design specifications and requirements.
• Identify and debug issues in the design and verification environment.
• Collaborate with the design team to identify and resolve coverage gaps.
• Mentor junior engineers and provide guidance on verification best practices.
• Utilize verification tools and methodologies to achieve high-quality verification results.
• Document and report verification progress and coverage status to stakeholders.

Desired Candidate Profile

• B.Sc. or M.Sc. in Computer Engineering, Electronics and Communications Engineering, or a related field, with 0 3 years of experience in hardware design verification.
• Advanced knowledge of SystemVerilog for creating testbenches and writing assertions.
• Advanced knowledge of UVM (Universal Verification Methodology) for building reusable verification environments.
• Proficiency in code coverage and/or functional coverage techniques.
• Good knowledge of integrating commercial VIPs into UVM testbenches.
• Good knowledge of RTL development and Verilog.
• Good knowledge of digital circuits, digital design/systems, and computer architecture.
• Knowledge of C, C++, and OOP.
• Knowledge of scripting languages such as Perl, Shell, and Tcl.
• Excellent command of the English language.
• Ability to work independently and as part of a team.
• Excellent presentation and communication skills.
• Knowledge of programming using SystemC is a plus.