HBM IP Subsystem End-to-End Solution Leader

You will own the end-to-end technical quality of the HBM memory subsystem (Memory Controller, PHY, and HBM KGSD) for our data center AI silicon — from RTL freeze through high-volume production. You define the quality gates, arbitrate the evidence, and close the loop between pre-silicon predictions and post-silicon reality. This is a high-influence, cross-functional role, partnering daily with design, DV, physical design, SI/PI, DFT/test, package, DRAM suppliers, and OSAT. (1) Pre-silicon quality check includes HBM MC, PHY, and HBM KGSD. (2) Post-silicon production readiness check includes PHY and HBM KGSD test quality.

Main Requirements and Qualifications

• 1. Experience in HBM(HBM3E, HBM4/4E, HBM5) IP subsystem end-to-end task covering HBM MC, PHY and HBM KGSD
• 2. Experience in designing and implementation of memory controller/PHY.
• 3. Familiar with the DRAM interface standards and memory technologies such as DDR or LPDDR or HBM.
• 4. Familiarity with DFI protocol of LPDDR or HBM.