PERSOL APAC
Integrated Circuit Layout Design Engineer
Skills
19 days ago
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Important information
Contract type:
Permanent
Location:
Singapore
Work mode:
Onsite
Published on:
5 October 2026
What they need
About the company:
We have partnered with a renowned global leader in information and communications technology (ICT) infrastructure and smart devices. They are providing full-stack, all-scenario solution for products and services carriers, enterprises, governments, and individual consumers worldwide.
Our client is looking for an Integrated Circuit Layout Design Engineer to join the team.
Responsibilities:
Design and deliver Physical Design Verification clean layouts for mixed signal and analog circuits in deep SubMicron CMOS technologies.
Review and analyze floor-plans and complex circuits alongside circuit designers to ensure accurate integration.
Run comprehensive design verification tools on circuit blocks to ensure correctness and adherence to specifications.
Collaborate with Circuit Designers to troubleshoot and solve complex technical issues
Contribute to enhancing layout flows for faster and higher-quality design processes.
Work closely with the circuit design team to exceed engineering specifications and performance expectations.
Leverage advanced CAD tools and mask design knowledge to deliver robust layouts that meet stringent matching, performance, area, and power requirements.
Qualifications:
Bachelor's degree in Electronic and Electrical Engineering, Microelectronics or related fields.
3~4 years of experience in analog layout design for blocks such as RFs, SerDes, ADCs, DACs, LDOs, PLLs, BGAP, amplifiers, etc.
At least 3 years of experience in layout and top-level IC integration within CMOS technologies (28nm, 16nm, 7nm).
Strong proficiency in custom and standard-cell based floor planning, as well as hierarchical layout assembly.
Deep understanding of key layout issues including IR drop, RC delay, electro-migration, self-heating, and cross-capacitance.
Proven experience recognizing failure-prone circuit and layout structures; familiar with analog and DFM standard methodologies.
High-level proficiency in interpreting CALIBRE DRC, ERC, LVS reports and addressing the resulting issues.
Expertise in MENTOR GRAPHICS or CADENCE layout tools.
Scripting skills in Perl, Python, or SKILL are a plus.
Strong interpersonal and communication skills with a collaborative approach to multi-functional teamwork.
Interested candidates, who wish to apply for the advertised position, please click on "Apply Now". We regret that only shortlisted candidates will be notified.
EA License No.: 01C4394
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