I/O Design Engineer

Job Overview

We are looking for an experienced I/O Circuit Design Engineer to design, develop, simulate, and optimize CMOS-based I/O circuits for advanced semiconductor technologies.

The ideal candidate will have strong expertise in transistor-level circuit design, I/O interface circuits, electrical reliability, and analog/mixed-signal simulation. The role involves developing robust I/O solutions that meet performance, power, signal-integrity, and reliability requirements across different process, voltage, and temperature conditions.

Key Responsibilities

1. I/O Circuit Design

• Design and develop transistor-level I/O circuits for standard and high-performance semiconductor interfaces.
• Develop I/O buffers, input receivers, output drivers, and associated interface circuitry.
• Work on CMOS I/O architectures supporting different operating voltages and interface requirements.
• Design and optimize circuits for parameters such as drive strength, propagation delay, output impedance, power consumption, and noise immunity.
• Support interface designs involving GPIO, LVCMOS, LVDS, and other parallel or high-speed interfaces, depending on project requirements.

2. Analog and Mixed-Signal Circuit Development

• Perform transistor-level schematic design and circuit implementation.
• Develop and optimize circuit architectures to meet electrical specifications.
• Analyze circuit behavior under different operating conditions and loading scenarios.
• Work on voltage-level compatibility, input thresholds, output characteristics, and signal integrity.
• Collaborate with analog, digital, library, and physical-design teams to deliver robust I/O IP.

3. Circuit Simulation and Verification

• Perform pre-layout and post-layout simulations using industry-standard EDA tools.
• Conduct corner simulations across process, voltage, and temperature (PVT) conditions.
• Perform Monte Carlo and mismatch simulations where required.
• Analyze timing, power, noise margins, leakage, and electrical performance.
• Debug simulation failures and optimize circuit performance against specifications.

4. Reliability and Robustness

• Understand and address ESD protection requirements and I/O reliability constraints.
• Analyze latch-up, electromigration, device stress, and voltage-tolerance concerns.
• Evaluate circuit robustness against process variations and operating conditions.
• Collaborate with reliability and qualification teams to address design-related issues.
• Support design optimization for reliable operation across applicable technology nodes.

5. Silicon Validation and Cross-Functional Collaboration

• Support silicon characterization, electrical validation, and correlation between simulation and measured results.
• Investigate silicon failures and identify potential circuit-level improvements.
• Work with layout engineers to address parasitics, coupling, matching, and physical implementation constraints.
• Collaborate with technology, product engineering, and validation teams through design release and qualification.

Mandatory Technical Skills

• Strong experience in transistor-level CMOS I/O circuit design .
• Hands-on experience designing input/output buffers, receivers, drivers, or related I/O interface circuits.
• Strong understanding of analog circuit fundamentals and semiconductor device physics.
• Experience with Cadence Virtuoso and Spectre or equivalent circuit design and simulation tools.
• Experience with SPICE-based simulations, including PVT corner analysis.
• Understanding of ESD, latch-up, signal integrity, noise margins, and electrical reliability.
• Experience in circuit optimization, debugging, and design validation.
• Familiarity with CMOS process technologies and their impact on circuit performance.

Preferred Skills

• Experience with standard I/O libraries or reusable I/O IP development.
• Exposure to GPIO, LVCMOS, LVDS, SSTL, HSTL, DDR I/O, or similar interface circuits.
• Experience with high-speed or high-voltage-tolerant I/O design.
• Knowledge of ESD protection circuits and I/O reliability qualification.
• Experience with post-layout simulation, parasitic extraction, and silicon correlation.
• Exposure to advanced CMOS, FinFET, or FD-SOI technologies.
• Experience with automotive-grade semiconductor products and reliability requirements.

Educational Qualifications

• Bachelor's or Master's degree in Electronics and Communication Engineering, Electrical Engineering, Microelectronics, or a related discipline.