Altera

About the role
Altera is looking for a hands-on Senior RTL Design Engineer to lead FPGA design and platform enablement for Altera development kits. This role spans architecture, Verilog/SystemVerilog implementation, Quartus flows and timing closure, board bring-up, interface validation, and system-level debug.
The ideal candidate can move comfortably from a system requirement or board schematic to a robust RTL implementation, then bring the design up on hardware and isolate issues across RTL, board, clocking, reset, memory, transceiver, and software boundaries.
What you will do
<ul>
<li>Define FPGA architecture, microarchitecture, block diagrams, interface behavior, register maps, clocking, reset strategy, and implementation plans for development-kit designs.</li>
<li>Design, RTL code, integrate, and maintain reusable synthesizable RTL using Verilog and SystemVerilog.</li>
<li>Translate board and system requirements into RTL features, diagnostics, loopback paths, manufacturing-test functions, and example designs.</li>
<li>Own the Altera FPGA development flow using Quartus Prime, including project setup, assignments and constraints, synthesis, fitting, static timing analysis, timing closure, configuration, programming, and release readiness.</li>
<li>Support board bring-up from first power-on through FPGA configuration, clock and reset validation, memory initialization, interface enablement, and production-readiness testing.</li>
<li>Validate interfaces on Altera development kits using internal and external loopback, protocol traffic, stress testing, interoperability testing, and corner-case testing.</li>
<li>Work on one or more of the following interface areas: PCIe, Ethernet, DDR/EMIF, high-speed serial transceivers, FMC, QSFP, USB, UART, I2C, SPI, GPIO, and other board peripherals.</li>
<li>Create RTL testbenches and simulation environments; use assertions, directed tests, and coverage-oriented techniques to improve design confidence.</li>
<li>Lead technical reviews, mentor engineers, communicate risks and status, and provide clear technical direction during cross-functional debug.</li>
<li>Collaborate closely with board engineers to review schematics, pin assignments, clock trees, reset and power sequencing, signal-integrity considerations, board revisions, and hardware constraints.</li>
<li>Partner with IP, silicon, firmware, board-test, validation, and applications teams to define interfaces, reproduce failures, and drive issues to root cause.</li>
</ul>
Qualifications:
<ul>
<li>Bachelor’s or master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.</li>
<li>10+ years of professional experience in FPGA RTL design, FPGA implementation, board bring-up</li>
<li>Strong expertise in Verilog and SystemVerilog for synthesizable RTL design.</li>
<li>Proven hands-on experience with the Quartus Prime or equivalent FPGA flow, including synthesis, fitting, timing analysis, timing closure, timing constraints, and hardware/software interaction.</li>
<li>Strong understanding of digital design fundamentals, including finite-state machines, pipelining, FIFOs, clock-domain crossing, reset-domain crossing, clock generation, reset sequencing, and multi-clock design.</li>
<li>Demonstrated ability to bring up and debug FPGA-based boards in a lab environment.</li>
<li>Strong analytical, written, verbal, and cross-functional communication skills.</li>
<li>Experience with Platform Designer/Qsys, Avalon-MM, Avalon-ST, AMBA AXI, DMA, memory-mapped registers, and streaming data paths.</li>
<li>Experience with high-speed interfaces and IP such as PCIe, Ethernet MAC/PCS/FEC, DDR4/DDR5/LPDDR, HBM, JESD, or FPGA transceiver solutions.</li>
<li>Experience with Questa, ModelSim, or equivalent simulation tools; lint, CDC analysis, formal checks, and assertion-based verification.</li>
<li>Experience leading technical reviews, coordinating external design partners, or mentoring junior engineers.</li>
</ul>
Good to have :
<ul>
<li>Experience reading schematics and working effectively with board, firmware, IP, and validation engineers.</li>
<li>Proficiency with Python and Tcl for build, test, regression, and lab automation; familiarity with Linux environments.</li>
<li>Experience with debugging system problems using simulation waveforms, Quartus reports, Signal Tap or equivalent FPGA debug facilities, JTAG, oscilloscopes, logic analyzers, protocol analyzers, and other lab equipment.</li>
<li>Working knowledge of several board and system interfaces, such as PCIe, Ethernet, DDR/EMIF, high-speed serial links, UART, SPI, I2C, GPIO, USB, or FMC.</li>
<li>Knowledge of Python, Tcl, or similar automation for builds, regressions, configuration, board testing, report generation, and lab workflows.</li>
</ul>
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

IP Logic Design Engineer

IP Logic Design Engineer

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