IP Physical Design Lead Engineer

Lead Analog IP PD tasks, such as floorplan, Bumpout, Power, IP integration
Execution of digital partitions: Synthesis to GDS, signoff (timing, physical verification, EMIR, Formal Equivalence, Low Power Verification)
Collaborate between PD, RTL team

Required Candidate profile

Exp on mixed signal IPs,such as PCIe/UCIE/DDR
Used Primetime, StarRC, Design Compiler, ICC
Constraints generation, STA, timing optimization/timing closure.
Exp of implementing design: synthesis to GDS