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IP Verification Engineer – ARM CPU Subsystem

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Onsite

IP Verification Engineer – ARM CPU Subsystem

LeadSoc Technologies Pvt Ltd

IP Verification Engineer – ARM CPU Subsystem

Skills

PythonGit

1 month ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

24 September 2026

What they need


IP Verification Engineer – ARM CPU Subsystem

Location: Bengaluru

Experience: 6–10 Years

Role Overview

We are looking for an experienced IP Verification Engineer with strong expertise in ARM CPU Subsystem (CPUSS) verification, CHI coherency, interconnect protocols, and ARM subsystem debug/bring-up . The role involves verification of complex ARM-based IPs and subsystems across simulation, debug, and pre-silicon/post-silicon bring-up.

Key Responsibilities

  • Develop and execute verification strategies for ARM CPU Subsystems (CPUSS) and related IPs.
  • Verify AMBA CHI coherency and interconnect protocols across complex subsystem configurations.
  • Develop and maintain SystemVerilog/UVM-based verification environments , testbenches, and test scenarios.
  • Validate cache coherency, ordering, transactions, QoS, interrupts, resets, and error scenarios .
  • Debug complex subsystem failures across RTL, simulation, waveform, and protocol levels .
  • Drive functional, protocol, and coverage closure for CPU subsystem verification.
  • Support ARM subsystem bring-up and debug , including root-cause analysis of integration issues.
  • Collaborate with RTL, Architecture, Firmware, Performance, and SoC teams to resolve design and verification issues.
  • Develop automation and debug utilities using Python, Tcl, or scripting languages .

Core Technical Requirements

  • 6–10 years of hands-on experience in IP/SoC Verification .
  • Strong experience in ARM CPU Subsystem (CPUSS) verification .
  • Deep understanding of AMBA CHI , coherency, interconnect, and transaction protocols.
  • Strong knowledge of cache coherency, snoop transactions, memory ordering, and system-level interactions .
  • Hands-on expertise in SystemVerilog and UVM .
  • Experience with subsystem debug, integration, and bring-up .
  • Strong skills in waveform/debug analysis, protocol debugging, and failure triage .
  • Experience with simulation and verification tools such as VCS, Xcelium, Verdi, or equivalent .
  • Strong understanding of ARM architecture and AMBA protocols .
  • Scripting experience in Python/Tcl/Perl is desirable.

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