Junior ASIC Engineer

Job Title: ASIC Engineer (Entry to Mid-Level)

Job Description:

We are seeking motivated ASIC Engineers to join our dynamic team. This role encompasses a range of responsibilities from foundational verification to physical design and synthesis. The ideal candidate will have a solid understanding of Verilog and SystemVerilog, with a keen interest in expanding their knowledge in ASIC design and verification.

Responsibilities:

Develop and verify ASIC designs using Verilog, SystemVerilog, and UVM methodologies.

Perform RTL design and SOCC verification.

Execute RTL synthesis to optimize performance, power, and area.

Develop and implement timing constraints for functional and test modes.

Participate in physical design activities, including RTL2GDS implementation (Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification).

Debug complex designs and high-speed interfaces (DDR, PCIe, ONFI).

Utilize lab equipment like Logic Analyzers and Oscilloscopes for debugging.

Develop and maintain test benches and verification environments.

Write and debug scripts in Tcl/Tk/Perl.

Work with Cadence tools (Innovus, Genus, Tempus) and Mentor Caliber.

Collaborate with cross-functional teams to achieve project milestones.

Contribute to the development and improvement of ASIC design and verification methodologies.

Required Skills:

Proficiency in Verilog, SystemVerilog, and UVM.

Strong debugging skills.

Experience in RTL design and SOCC verification.

Knowledge of ASIC design and verification flows.

Understanding of physical design concepts (RTL2GDS).

Experience with synthesis and STA.

Ability to work with Cadence and Mentor tools.

Good communication and teamwork skills.

Scripting experience (Tcl/Tk/Perl) is a plus.

Experience:

0-7 years of relevant experience.