Layout Design Engineer

Senior Custom IC Layout Engineer – SRAM / Memory
Location: Santa Clara, CA
Workplace: Onsite
Experience: 10+ years
Employment Type: Full-Time

Job Summary
We are looking for a highly experienced Senior Custom IC Layout Engineer to join our semiconductor design team in Santa Clara, CA.
The ideal candidate will have 10+ years of custom IC layout experience, with strong expertise in SRAM, memory macros, memory compilers, and full-custom memory IP. You will be responsible for the complete physical layout lifecycle, from floorplanning and custom layout development through physical verification and tapeout.
This role requires hands-on experience with Cadence Virtuoso, Calibre/ICV, advanced CMOS technologies, SRAM layout, physical verification, and advanced-node design challenges.

Key Responsibilities

• Own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros.
• Develop and optimize floorplans for SRAM and memory blocks, including:
• Array layout
• Periphery placement
• Power grids
• Routing channels
• Macro assembly
• Perform and debug DRC, LVS, ERC, antenna, and other physical verification checks.
• Support EM/IR analysis, power integrity, density, fill, DFM, dummy insertion, and layout-dependent effects through tapeout.
• Work closely with circuit designers to translate schematics into high-quality custom layouts while maintaining:
• Matching
• Symmetry
• Shielding
• Parasitic targets
• Reliability requirements
• Collaborate with PnR and physical integration teams to resolve top-level D

Pay: $45.00 - $65.00 per hour

Expected hours: 40.0 per week

Location:

• Santa Clara, CA 95055 (Required)

Work Location: In person