Layout Engineer

Design analog and high-speed circuits including Transmitter & Receiver equalization (FFE/CTLE/DFE), op-amps, Bandgap references, regulators, charge pumps, ADC, PLL, DLL, CDR and other precision blocks in advanced FinFET process nodes, preferably TSMC 16nm and lower nodes. Conduct simulations across PVT corners, collaborate with layout and verification teams, and ensure ESD-aware circuit design. Optimize circuits for power, performance, and area.

• Circuit architecture, schematic design for DDR & Serdes PHY IPs.
• Simulation across PVT corners and worst-case analysis
• Collaboration with layout, verification, and reliability teams
• ESD-aware circuit design and protection
• Design for manufacturability and yield enhancement
• Documentation and IP integration support
• Prior experience with  Cadence ADE/Artist, Spectre, EMIR & reliability flow

Roles and Responsibilities
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.