Layout Engineer ( SRAM)

Join Quest Global and be part of a team shaping the future of semiconductor innovation!

We are looking for an experienced Sr. SRAM Layout Design Engineer with strong expertise in custom memory layout design and advanced process technologies.

🔹 Key Responsibilities:

• Own end-to-end SRAM custom layout implementation including bitcell arrays, memory periphery, test structures, and memory macros.
• Drive floorplanning, macro assembly, routing strategy, and power-grid implementation.
• Perform and debug DRC, LVS, ERC, antenna, and physical verification checks using Calibre/ICV or equivalent tools.
• Collaborate closely with circuit, integration, CAD, and foundry teams to ensure successful tapeout.
• Support advanced-node requirements including EM/IR, DFM, density/fill, shielding, matching, and reliability analysis.
• Mentor engineers and contribute to layout methodology improvements.

🔹 What We're Looking For:

• 10+ years of Custom IC Layout experience
• Strong background in SRAM/Memory IP Layout Design
• Expertise in Cadence Virtuoso and Calibre/ICV verification flows
• Experience with FinFET/GAA technologies (5nm, 3nm, or below)
• Deep understanding of advanced-node layout challenges and tapeout requirements
• Strong collaboration and leadership skills

🌟 Why Join Quest Global?

• Work on cutting-edge semiconductor and memory technologies
• Collaborate with world-class engineering teams
• Opportunities for technical growth and leadership
• Be part of innovative programs driving next-generation silicon products

📍 Location: Santa Clara,CA

📧 Interested candidates can apply directly or share their resume at [email protected] .

With Regards

Shashank Verma