Lead DDR Verification Engineer

Job highlights

• . At least 7 years of of relevant experience. Updating / debugging TCL code embedded in a variety of tools,such as simulator,waveform-viewer,formal verification,in-house interpreter,etc
• Experience with revision control like git or GitHub .

We re looking for a candidate who has the following skillsets:

• Extensive knowledge of Perl and Python
• Knowledge of dependency-checking via make, SCons
• LSF or other batch-queuing system (e.g. Grid, PBS, Open Lava), and script integration
• Using REST API (e.g. Jenkins, Jira) from Perl, Python
• Migrating scripts, script-libraries to different Linux OS releases
• Knowledge of SQL, relational database engines like MariaDB or PSQL, and integration with Perl/Python
• Knowledge of web technologies: Basic Apache setup, PHP, Javascript/Jquery, RSS automation

These skillsets and knowledge would also be desirable:

• BS/MS - Electrical / Computer Engineering.
• At least 7 years of of relevant experience.
• Updating/debugging TCL code embedded in a variety of tools, such as simulator, waveform-viewer, formal verification, in-house interpreter, etc.
• Knowledge of Verilog, SystemVerilog testbenches; some familiarity with methodologies like OVM or UVM; incorporate DPI or PLI models
• Some IT knowledge: NFS, memory/CPU profiling, NIS/DNS/LDAP, SMTP, syslog, cron, etc
• Jenkins install / configuration / management
• Module-files and modulecmd to manage tools and tool-versions
• Cloud deployment/maintenance: Amazon Web Services, MS Azure, IBM Cloud
• Experience with revision control like git or GitHub
• The position is based in Austin/San Jose/Bangalore (India)