Lead Design for test (DFT) Engineer

🚀 Hiring: Lead DFT Engineers

We are looking for experienced DFT Engineers to drive end-to-end test architecture and implementation for complex ASIC/SoC designs .

📌 Experience: 7 to 14yrs

🔍 Role Overview:

In this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle. You will work closely with design, verification, physical design, and silicon validation teams to ensure high product quality and test coverage.

🛠️ Key Responsibilities:

• Define and implement DFT architecture for large, complex SoCs/ASICs
• Own end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary Scan
• Perform Scan insertion, ATPG pattern generation, compression, and fault grading
• Develop and maintain DFT specifications and ensure compliance throughout the design cycle
• Integrate and verify DFT logic at RTL and gate-level (GLS)
• Collaborate with verification teams for pattern simulation, validation, and debug
• Work closely with physical design teams to meet timing, power, and area constraints
• Debug silicon bring-up issues and support ATE test pattern validation
• Drive improvements in DFT methodologies and flows
• Mentor junior engineers and provide technical leadership

📚 Required Skills:

• Strong expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniques
• Hands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalent
• Solid understanding of RTL design, synthesis, and verification flows
• Familiarity with STA and physical design constraints related to DFT
• Experience in silicon bring-up and ATE test pattern generation
• Strong debugging and analytical skills

💡 What We’re Looking For:

• Proven ability to own and drive DFT closure for complex chips
• Strong collaboration across cross-functional teams
• Leadership mindset with mentoring capabilities
• Excellent communication and problem-solving skills