Lead DFT Engineer

Role Summary

We are seeking an experienced Design-for-Test (DFT) Engineer at the Senior Member of Technical Staff (SMTS) level with over 10 years of industry experience. The candidate will be responsible for architecting, implementing, and validating advanced DFT solutions across complex SoCs. The role requires strong expertise in MBIST, SCAN Insertion, ATPG and simulation (RTL & GLS), and close collaboration with PnR teams to ensure testability and design closure.

Key Responsibilities

• Define and implement DFT architecture including Scan, MBIST, and Test Access Mechanisms.
• Lead Scan Insertion, ATPG Pattern Generation
• Develop and integrate MBIST solutions for embedded memories (SRAM/MRAM/ROM).
• Perform RTL-level DFT verification and debug.
• Execute and debug Gate-Level Simulations (GLS) with SDF back-annotation.
• Validate Scan Patterns, MBIST controllers, and test protocols across multiple modes (functional/scan/mbist test).
• Redundancy analysis (RA) flows
• Fuse/OTP programming for repair implementation
• Integration of repair signatures into test and bring-up flows
• Drive ATPG pattern generation, validation, and coverage improvement.
• Analyze failure logs and debug issues during simulation and silicon bring-up.
• Collaborate closely with Physical Design (PnR) teams for:
• Scan chain stitching and reordering.
• Write SDC for timing closure for test paths.
• Understand physical impacts of DFT (congestion, timing, power).
• Support silicon bring-up, ATE debugging, and manufacturing test strategies.

Required Qualifications

• BSEE/MSEE in Electrical Engineering with 10+ years of strong hands‑on experience in JTAG, Scan, Memory BIST, and ATPG
• Proficient in SystemVerilog and UVM‑based verification environments.
• Expertise with ATPG and MBIST tools, particularly Tessent (mandatory).
• Strong proficiency in testbench development, simulation, and debug.
• Experience in post‑silicon failure analysis, diagnostics, and debug.
• Ability to work with ATE patterns and perform gate‑level simulations.
• Skilled in scripting and automation using Tcl, Python, and Shell.
• Experience in RTL development and functional verification of logic circuits is an added advantage.

Pay: ₹646,538.13 - ₹2,029,091.97 per year

Work Location: In person