Lead Full Chip Floorplan Design Engineer

Job Summary

We at AECG SSD Custom Silicon are seeking a highly motivated and experienced Full-Chip Floorplan Engineer to drive physical implementation planning for complex SoCs and ASICs. The candidate will be responsible for developing and optimizing full-chip floorplans, partitioning strategies, power planning, interconnect planning, and physical architecture to achieve aggressive PPA (Power, Performance, Area) targets while ensuring design convergence and manufacturability.

The role requires close collaboration with Architecture, RTL, Physical Design, DFT, Power, Package, and Verification teams throughout the SoC development lifecycle. Industry full-chip floorplanning activities commonly include die shaping, macro placement, IO planning, power-domain planning, pin assignment, feedthrough planning, and physical integration strategy development.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

Key Responsibilities

• Full-Chip Floorplanning
  • Develop and own top-level SoC floorplan architecture.
  • Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning.
  • Perform macro placement and optimization for timing, congestion, power, and thermal considerations.
  • Drive floorplan refinement through design milestones.
  • Define floorplan topology for large-scale SoCs containing multiple subsystems, hard IPs, memories, and third-party IPs.
• Physical Architecture Planning
  • Develop and optimize:
    • Power domain strategy
    • Voltage island planning
    • Power grid architecture
    • Isolation and retention planning
    • Feedthrough strategy
    • Repeater insertion strategy
    • Boundary and channel planning
• IO and Package Planning
  • Define chip-level IO placement strategy.
  • Collaborate with package teams on bump map optimization.
  • Drive chip-package co-design activities.
  • Optimize high-speed interface placement (PCIe, SerDes, C2C, DDR, Ethernet, etc.).
• Interconnect Timing Planning
  • Develop timing-driven floorplans.
  • Define physical partitions and timing boundaries.
  • Establish timing budgeting methodology across subsystems.
  • Plan clock distribution architecture and clock-domain placement.
• Congestion, Power Thermal Optimization
  • Identify congestion hotspots and implement mitigation strategies.
  • Drive early power estimation and thermal-aware floorplanning.
  • Optimize placement for PPA convergence.
  • Support EMIR-aware floorplan planning.
• Cross-Functional Collaboration
  • Work closely with Architecture teams
  • RTL designers
  • Physical Design teams
  • DFT engineers
  • Packaging teams
  • Power methodology teams
  • Verification teams
  • Review subsystem floorplans and ensure full-chip integration readiness.
• Methodology and Automation
  • Develop scripts and automation for floorplan generation and analysis.
  • Drive methodology improvements and best practices.
  • Enable scalable planning methodologies for next-generation SoCs.

Preferred Experience

• 12+ years of ASIC/SoC Physical Design experience with strong expertise in Full-Chip Floorplanning.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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