Lead Memory Modeling Engineer

Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications.

Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart.

At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect.

Job Purpose

The Memory Layout Lead builds and leads the memory layout team in Vietnam and owns the physical implementation of Silvaco’s memory IP portfolio — SRAM, DPRAM, ROM, and Register File. The role combines people leadership — resourcing, development, and performance of the memory layout engineers — with direct technical ownership of the layout methodology and sign-off quality, ensuring that every memory deliverable is floorplanned, implemented, and released to the required density, performance, and reliability targets, on time and to specification.

This is a working leadership role. The Lead is expected to remain hands-on in layout execution while carrying responsibility for the team’s output, standards, and growth.

Key Roles & Responsibilities

Team Leadership & People Development

• Supervise the memory layout engineers — allocate work across the memory portfolio, estimate effort, balance load against the project schedule, and own the technical quality of what the team releases.

• Assist the management team with personnel development: set individual development plans, run regular one-to-ones, give structured technical feedback, and identify training and skill gaps within the team.

• Build the onboarding and training path for new memory layout engineers and interns, and mentor engineers in advanced layout methodologies and best practices.

• Ensure company policies and processes are adhered to within the team — working hours, documentation and release discipline, security and IP-handling rules, and quality procedures.

• Support recruitment for the memory layout team: define technical screening criteria, review CVs, conduct technical interviews, and make level and hiring recommendations to the Memory Design Manager and HR.

• [M3] Own the team’s objectives, headcount plan, and performance cycle — set and calibrate individual objectives, deliver mid-year and annual performance reviews, make promotion and merit recommendations, and manage under-performance in cooperation with HR.

• [M3] Own resource planning and prioritisation across concurrent memory projects, including forecasting capacity, escalating shortfalls, and negotiating scope and schedule with the Memory Design Manager and global stakeholders.

Layout Architecture & Methodology

• Own the layout strategy for the memory portfolio — floorplan architecture, array organisation, tiling and abutment scheme, power grid, and top-level assembly for memory instances and compilers.

• Define and maintain the memory layout methodology: design guidelines, layer and pitch conventions, review checklists, sign-off criteria, and release standards adopted by the whole Memory team.

• Drive porting and re-targeting of memory layouts to new process nodes and foundries, including design-rule impact assessment, leaf-cell re-floorplanning, and area-reduction strategy under tight constraints.

• Conduct technical reviews and benchmarking of layout deliverables, and drive root-cause analysis and solutions for physical design challenges.

Layout Execution & Signoff

• Own the layout design and verification of critical memory IP blocks, including floorplanning, placement, routing, and signoff.

• Own pitch-matched leaf-cell and array layout, ensuring the implementation scales correctly across the full configuration range supported by the compiler.

• Drive physical verification to closure — DRC, LVS, ERC/VERC, antenna, ResCheck/CapCheck, DFM and density — and resolve complex multi-level violations under schedule pressure.

• Own parasitic and reliability closure: RC extraction, EMIR analysis, IR-drop and electromigration resolution, and power-distribution optimisation to clean sign-off.

Automation & Methodology

• Develop and implement automation scripts (Perl/Python/TCL/Shell/SKILL) to accelerate layout cycles and improve quality, and integrate them within the memory compiler / view-generation environment to improve robustness and turnaround time.

• Introduce and implement methodology improvements that enhance layout quality and overall team efficiency.

Collaboration & Support

• Work in close cooperation with Memory Design, Modeling, DFT, Physical Design, and CAD teams to deliver on time and according to required specifications.

• Collaborate with layout leads, CAD, and process teams to optimise layout flows and methodologies, and interface with foundry and IP partners on PDK, bitcell, and design-rule questions.

• Provide technical input on project planning and risk assessment, and present technical findings, risks, and solutions to internal and external stakeholders.

• Generate the required documentation, support consumers of the layout deliverables, and contribute to the validation and debugging of fabricated silicon.

Essential Requirements

• BS/MS in Electronics Engineering, Telecommunications, Microelectronics, Computer Engineering, Physics, or a related field.

• Minimum 8 years of hands-on custom layout design experience, of which at least 4 years on memory IP (SRAM, DPRAM, ROM, Register File, or TCAM). (M3: minimum 10 years, including demonstrated ownership of a layout team.)

• Demonstrated leadership of a layout team or squad: allocating work, reviewing deliverables, developing engineers, and owning quality and release. Formal line-management experience is required at M3 and strongly preferred at M2.

• Ownership of the physical implementation of an IP or compiler family through to tape-out.

• Proficient with layout capture tools (Cadence Virtuoso or equivalent).

• Proficient with layout verification and extraction tools (Calibre, ICV, PVS, StarRC, QRC or equivalent).

• Hands-on EMIR / IR-drop and electromigration analysis, and power-distribution optimisation.

• Familiarity with advanced process nodes (e.g., 5nm, 3nm) and associated challenges.

• Strong scripting/programming skills (Perl, Python, TCL, Shell, SKILL) on Unix/Linux.

• English Language Proficiency: Fluency, written and verbal.

• Strong communication, analytical, and problem-solving skills.

Desirable Requirements

• Master’s degree in Electronics / Microelectronics Engineering.

• Hands-on experience with memory compilers and view-generation flows.

• Experience defining layout methodology, checklists, or training programmes for a team.

• Experience building a team from a small base — hiring, onboarding, and establishing working practices in a new capability.

• Understanding of memory architectures (SRAM/ROM/Register File) and of the circuit constraints that shape memory layout.

• Familiarity with standard views (LEF, GDS, CDL) and their consumers in Physical Design and STA.

• Experience with advanced FinFET process nodes.

• Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes.

The Memory Senior Modeling Engineer owns the generation, validation, and delivery of the complete set of memory views and models for Silvaco’s memory IP portfolio. As a senior technical contributor within the Memory Design team, the role ensures that every consumer of memory deliverables — Physical Design, Static Timing, DFT, and design teams — is supported by accurate, silicon-correlated, and on-time models, while continuously improving the modeling and quality-assurance methodology.