Lead Server Performance Architect

Job Summary

Lead Server Performance Architect: AMD is looking for an outstanding technical contributor to help architect, validate optimize performance of new features through full chip simulation emulation platforms for AMD-based next-generation servers. As a passionate and dedicated Server Systems Performance Architect in the Server Performance Group, you will identify new opportunities to optimize server silicon for throughput and latency by identifying opportunities across all parts of silicon micro architecture and design spanning CPU, Data Fabric, Memory subsystem and IO. You will validate and analyze performance of various design features in pre silcon design env and correlate the profiling data with AMD performance model and eventually AMD silicon. You will quantify and isolate performance bottlenecks and share the insights to help new drive features into the next generation of server CPUs. The ideal candidate is expected to be well informed on latest trends in server design and verification, have a well-rounded understanding of performance requirements for server market and be able to quickly ascertain, in a data-driven manner, how next generation server CPUs and platforms should be engineered to support those needs

Key Responsibilities

Team Leadership

• Lead and mentor a high-performing team of performance verification engineers.

• Foster a culture of innovation, technical rigor, and continuous improvement.

• Provide strategic direction across multiple concurrent verification programs.

  Program Leadership

• Define and execute the performance verification strategy for high-performance x86 server CPU.

• Collaborate with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs.

• Ensure timely delivery of simulation/emulation results, and optimization feedback loops.

  Performance Analysis Correlation

• Develop and execute performance verification plans targeting IPC, latency, throughput, and power efficiency.

• Capability to debug performance outliers thru Performance Monitoring Counters (PMC).

• Drive correlation between RTL and performance models, ensuring architectural intent is met.

• Analyze performance bottlenecks using simulation, emulation, and silicon data.

  Toolchain Methodology

• Build and maintain scalable, modular performance verification infrastructure.

• Lead emulation-based performance setup and debug, enabling early performance validation.

• Integrate performance regression, profiling, and analysis flows using industry-standard and custom tools.

• Collaborate with compiler and OS teams to ensure software stack alignment with hardware performance goals.

  AI-Driven Infrastructure

• Drive the development of AI/ML-based infrastructure to automate performance analysis, anomaly detection, and efficiency improvements.

• Leverage data-driven techniques to optimize verification coverage and reduce debug cycles.

  Cross-Functional Collaboration

• Partner with x86 architecture, RTL design, physical design, and software teams to ensure performance targets are met.

• Influence design decisions through data-backed performance insights.

  Stakeholder Management

• Align verification goals with business and product roadmaps.

• Communicate performance status, risks, and trade-offs to executive leadership and stakeholders.

  Industry Awareness

• Stay current with trends in CPU architecture, performance modeling, and verification technologies.

• Evaluate and adopt emerging tools and techniques to maintain a competitive edge.

  Preferred Experience

• 15+ years of industry experience with performance modeling and simulation tools (e.g., cycle-accurate simulators, emulators) with strong background in CPU microarchitecture, performance analysis, and system-level performance verification.

• Proven leadership in managing large, cross-functional engineering teams.

• Familiarity with PMC DV, latency and throughput validation, emulation platforms, and performance debug flows.

• Deep understanding of x86 ISA, microarchitecture, and performance metrics.

• Experience in developing performance test suites, performance triage tools, and simulation/emulation infrastructure.

• Expertise in performance analysis tools, correlation techniques, and workload optimization.

• Strong analytical and problem-solving skills with a data-driven mindset.

• Deep knowledge of modern out-of-order CPU cores, memory subsystems, and performance modeling is a plus.

• Experience with ML/AI techniques/frameworks for performance triage, infrastructure automation and prediction is a plus.

• Exposure to high-performance computing (HPC), virtualization, or server-class CPUs.

• Background in hardware/software co-design and performance-aware compiler optimizations.

• Familiarity with pre-silicon and post-silicon debug methodologies.

  Position Requirements

• Should have executed Emulation based functional and performance verification for multimillion gate SoC designs

• Should have strong exposure to RTL coding and SOC bringup debug

• Exceptional foundation in systems architecture, cutting across CPU, memory, storage and I/O subsystems

• Experience with hardware performance counter monitoring tools

• Should have exposure to performance profiling tools, preferably x86 based (e.g. linux perf, Windows perfmon)

• MS/PhD in Computer Engineering / relevant coursework / thesis

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.