Lead/Manager RTL Design

Roles and Responsibilities:

• Lead the architecture, design, and development of complex, high-speed digital systems using FPGAs.
• Own end-to-end RTL design lifecycle (specification, design, coding, simulation, synthesis, timing closure, and validation).
• Provide technical leadership and mentorship to a team of FPGA engineers; review designs and enforce best practices.
• Drive system architecture decisions, interface definitions, and design trade-offs for performance, power, and cost.
• Collaborate with cross-functional teams (hardware, software, systems, validation) to define requirements and verification strategies.
• Integrate and optimize high-speed IPs such as PCIe, 10G/25G Ethernet, JESD, GT/MAC, and memory interfaces.
• Lead design verification planning, including testbench development, simulation, and hardware validation.
• Oversee board bring-up, debugging, and performance tuning using lab equipment.
• Identify and resolve complex issues during development, testing, and field deployment.
• Ensure documentation, coding standards, and design processes are followed across projects.
• Interface with external stakeholders (including labs such as DRDO) for project execution and technical alignment.

Required Skills:

• Strong expertise in digital design fundamentals and high-speed FPGA system design.
• Extensive experience with high-speed interfaces: PCIe, 10G/25G Ethernet, JESD, HS DAC/ADC.
• Proven experience in architecting and implementing complex FPGA-based designs.
• Hands-on experience with high-end FPGAs from Altera (Intel), AMD (Xilinx), and Microchip.
• Experience working on projects with DRDO labs or similar defense/research organizations.
• Strong electronics fundamentals and system-level understanding.
• Expertise in timing closure, CDC, constraints, and performance optimization.
• Strong debugging skills using lab equipment (Oscilloscope, Logic Analyzer, DMM).
• Excellent leadership, communication, and stakeholder management skills.

Preferred Skills:

• Proficiency in VHDL, Verilog/SystemVerilog, Python, and TCL scripting.
• Experience with PCIe, 10G/25G Ethernet, AXI-4, and high-speed transceivers.
• Exposure to verification methodologies (UVM/advanced simulation environments).
• Experience with FPGA toolchains (Vivado, Quartus, Libero) and CI/CD flows.
• Knowledge of embedded processors (SoC FPGAs) and firmware/software integration.