Lec Cad Engineer, Lead

Job Summary

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

As a Staff CAD Engineer specializing in Logical Equivalence Check (LEC), you will be a key contributor to Qualcomm's formal verification infrastructure. You will work within the GCAD (Global CAD) organization, collaborating closely with design, synthesis, and implementation teams to ensure functional correctness of SoC designs across all stages of the ASIC design flow. You will leverage industry-leading EDA tools such as Cadence Conformal LEC, Conformal ECO, and Synopsys Formality to deliver high-quality, silicon-ready designs.

Key Responsibilities

• Own and drive the end-to-end LEC flow including RTL-to-initmap, RTL-to-initopt, RTL-to-finalopt, gate-to-gate (G2G), and ECO verification runs.
• Debug and resolve Non-Equivalences (NEQs), aborts, unmapped points, and incomplete verifications across complex SoC subsystems (e.g., APSS, DDRSS, GFX, Modem).
• Develop and maintain LEC scripts, dofiles, and automation infrastructure using Tcl, Perl, Python, or Shell scripting.
• Collaborate with synthesis engineers to integrate LEC into the synthesis flow using Cadence Genuswrite_do_lecand Synopsys DCwrite_formality_scriptinterfaces.
• Support Power-Aware Formal Verification (PA-FV) using UPF/CPF-based flows with Conformal Low Power (CLP) and Synopsys Formality with UPF.
• Triage and resolve LEC-related JIRA tickets and provide technical guidance to junior engineers.
• Contribute to LEC flow improvements, recipe development (abort recipes, compare recipes), and methodology enhancements across both Conformal and Formality platforms.
• Participate in design handoffs, FEQOR portal sign-offs, and cross-functional reviews.
• Evaluate and qualify new EDA tool versions and features from Cadence and Synopsys vendors.
• Mentor junior and senior engineers on LEC methodology, debug techniques, and best practices across both tool ecosystems.

Education Requirements

• Required: Bachelor's degree in Electrical Engineering, Computer Engineering, VLSI Embedded Systems, or equivalent.
• Preferred: Master's degree in Electrical Engineering, Computer Engineering, or VLSI Embedded Systems.

Required Skills Experience

• 5+ yearsof hands-on experience in ASIC/SoC CAD engineering with a focus on formal verification and LEC.
• Deep expertise in Cadence Conformal LEC (RTL-to-gate, gate-to-gate, ECO verification).
• Strong hands-on experience with Synopsys Formality
• Strong understanding of ASIC design flows from RTL synthesis through GDS, including synthesis (Cadence Genus / Synopsys DC), place route, and ECO flows.
• Proficiency in debugging NEQs, aborts, and unmapped key points in complex hierarchical designs.
• Experience with Power-Aware LEC / Conformal Low Power (CLP) using UPF/CPF.
• Solid scripting skills in Tcl, Perl, Python, and/or Shell (Bash/CSH).
• Familiarity with RTL languages (SystemVerilog / Verilog / VHDL).
• Experience with UNIX/Linux environments and large-scale compute grid infrastructure (LSF, SGE).
• Strong analytical and problem-solving skills with attention to detail.
• Experience with Sequential Equivalence Checking (SEC) tools such as Cadence JasperGold SEC App or Synopsys VC Formal.
• Knowledge of DFT (Design for Test) constraints and their impact on LEC flows in both Conformal and Formality.
• Familiarity with Smart LEC (SLEC), SVP operators, and advanced abort resolution techniques.
• Experience with FEQOR portal and Qualcomm's internal handoff and sign-off processes.
• Exposure to multi-tool LEC strategies knowing when to use Conformal vs. Formality based on design complexity and synthesis tool chain.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.