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Low Latency Engineer

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Onsite

Low Latency Engineer

Entec Partners

Low Latency Engineer

3 months ago

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Important information


Contract type:

Permanent

Location:

New York, NY, USA

Work mode:

Onsite

Published on:

15 August 2026

What they need


We are seeking highly skilled C++ engineers with extensive experience in high-frequency trading systems to join one of the leading proprietary trading house specialized in solving market inefficiencies, identifying opportunities based on volatility arbitrage and delta1 strategies and providing liquidity to the markets.

About the Role

As a Low Latency Engineer, you’ll work closely with highly skilled traders, quant researchers, and C++ engineers. You will have direct, immediate, and large-scale impact on the business, by making sure their trading algorithms and architecture are highly competitive in a world where latency is key.

These engineers are hired for their passion and knack for coding and solving technical challenges. They love to think outside the box and see their code in production as little as hours after the initial idea was coined.

Responsibilities:

As a Low Latency Engineer, no two days will be the same. Your main responsibility will be bringing latency down by an extra micro- or nanosecond wherever possible.

Understand and discuss requirements with team members, i.e. traders and researchers

Identify and eliminate code inefficiencies, continuously optimize for minimal latency in high-throughput network applications, ensuring our competitiveness in an ever-improving market

Requirements:

  • Extensive experience in developing C++ low-latency systems within a trading environment, with a deep understanding of modern computer architecture and high-performance code design.
  • Expertise in the architecture, configuration, and optimization of both network and server components, including network cards (e.g., Arista, Cisco Nexus, Cisco Fusion); knowledge of switches is a plus.
  • Proficient in using hardware performance counters and profiling tools to enhance application performance; familiarity with FPGA collaboration is a plus.
  • Solid experience with fast-packet processing in user space and kernel-bypass technologies

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