Brillify Tech Inc.

Position Summary
We are looking for a Mask Design Engineer to develop and maintain semiconductor layouts for optical communications products, including VCSELs, photodiodes, and highly integrated addressable arrays. You will translate device and process requirements into manufacturable physical layouts and reliable mask data, working closely with R&amp;D and international engineering teams. This role is remote from Taiwan and requires clear written and spoken communication in English.
Key Responsibilities
<ul>
<li>Develop physical layouts and complete mask sets for VCSELs, photodiodes, addressable arrays, test structures, and new optical communication devices.</li>
<li>Own layout implementation and mask data preparation from early device concepts through design reviews, verification, and production release.</li>
<li>Build manufacturable layouts in Cadence, including device geometry, high-density interconnects, metal routing, pads, and alignment features.</li>
<li>Run and resolve automated Design Rule Checks (DRC); support Layout Versus Schematic (LVS) and other verification flows where applicable.</li>
<li>Design process monitor structures, test patterns, and characterization layouts with device and process teams to support process development, control, yield improvement, and reliability investigations.</li>
<li>Work with R&amp;D, process engineering, manufacturing, and external foundry partners to interpret process requirements and resolve layout, manufacturability, and integration issues.</li>
<li>Participate in design and layout reviews, assess layout-related risks, and support root-cause analysis and corrective actions when issues arise.</li>
<li>Maintain reusable cells, layout guidelines, verification practices, and automation that improve consistency, quality, and design turnaround time.</li>
<li>Manage mask revisions and release documentation with clear revision history, configuration control, and traceability.</li>
</ul>
Required Qualifications
<ul>
<li>Bachelor’s or Master’s degree in Electrical Engineering, Physics, Photonics, Microsystems Engineering, Semiconductor Engineering, or a related field.</li>
<li>Several years of experience in semiconductor mask layout or IC physical layout design.</li>
<li>Strong hands-on experience with Cadence layout tools.</li>
<li>Practical experience with automated DRC and production mask set preparation or release.</li>
<li>Good understanding of semiconductor fabrication processes and how critical dimensions, overlay, alignment, and layout-for-manufacturing considerations affect a design.</li>
<li>Familiarity with GDSII, mask data preparation, and tape-out or foundry handoff workflows.</li>
<li>Strong attention to detail, organized revision management, and effective written and verbal communication in English.</li>
</ul>
Preferred Qualifications
<ul>
<li>Experience with VCSELs, photodiodes, III-V semiconductor devices, or related optoelectronic technologies.</li>
<li>Experience designing addressable arrays, high-density interconnects, or complex metal routing.</li>
<li>Experience creating process control monitor structures, test keys, or process characterization patterns.</li>
<li>Experience working directly with semiconductor foundries or cross-functional process and device teams.</li>
<li>For workflows that use KLayout, experience with Python for layout generation, verification, or data analysis.</li>
</ul>

Mask Design Engineer

Mask Design Engineer

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