Memory Design Automation - Memory Modeling

• Lead the development and coding of front-end design kits, including memory RTL models, ATPG models, and other views essential for ASIC design flow.
• Create and optimize automation flows and scripts using Perl or Python to enhance workflow efficiency and ensure model accuracy.
• Utilize EDA tools from vendors such as Synopsys and Mentor Graphics to validate model correctness.
• Maintain up-to-date knowledge of current modeling standards and advancements from EDA tool vendors to enhance memory IP performance and meet the latest ASIC design flow requirements.
• Ensure the functional correctness of memory circuits by validating them against memory models.
• Collaborate with the memory design team and compiler development team to deliver comprehensive memory front-end design kits.
• Troubleshoot and resolve model issues in collaboration with RTL designers, design verification teams, DFT teams, and tool vendors.

Job Requirements

• Bachelor’s Degree or higher in Electrical Engineering, Electronics Engineering, or related discipline.
• Knowledge of high performance, low power SRAM/ROM and VLSI design is an added advantage. Experience with EDA tools will be helpful.
• Proficient with Perl, Shell, Python, C/C++ languages, knowledge with AI machine learning algorithm and infrastructure is an added advantage.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Understanding of liberty timing syntax is a plus.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required
• Experience with EDA tools will be helpful:
• DFT: Logicvision, Tessent, Fastscan
• Synthesis: Design compiler, Genus
• Simulation tools:VCS, QuestaSim, NC
• STA tools such as PrimeTime
• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Interested candidates may apply through the application system. We regret to inform only Shortlisted candidates will be notified.

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