Memory Design Lead

We are looking for an experienced Memory Design Lead with 10+ years of hands-on experience in SRAM and/or MRAM design to lead the development of advanced Memory IPs from architecture definition to silicon validation and production release.

The ideal candidate should have strong expertise in Memory Architecture, Custom Circuit Design, Sense Amplifiers, Memory Peripheral Circuits, PVT/Monte Carlo analysis, memory margin analysis, silicon debug, characterization, and PPA optimization.

Key Responsibilities

• Own complete Memory IP development lifecycle from architecture and circuit design to silicon validation and production.

• Define and review memory architecture and circuit implementation.

• Design and optimize memory peripheral circuits such as:

• Sense Amplifiers

• Write Drivers

• Row/Column Decoders

• Timing & Control Logic

• Reference Generation Circuits

• Drive Power, Performance, and Area (PPA) optimization.

• Ensure robust operation across PVT corners and process variations.

• Perform Read/Write Margin, Retention, Variability and Monte Carlo analysis.

• Lead silicon bring-up, characterization, failure analysis and silicon debug.

• Drive simulation-to-silicon correlation and yield improvement.

• Work closely with Architecture, Physical Design, DFT, Product Engineering and Technology teams.

• Provide technical leadership and mentorship to memory design engineers.

• Support production release and memory IP qualification.

Mandatory Skills

• 10+ years of relevant Memory Design experience
• Strong hands-on experience in SRAM and/or MRAM Design
• Memory Architecture
• Custom Circuit Design
• Sense Amplifier Design
• Write Driver Design
• Decoder Design
• Timing & Control Circuits
• Reference Generation Circuits
• PVT Analysis
• Monte Carlo / Statistical Analysis
• Memory Margin Analysis
• Silicon Debug & Characterization
• Simulation-to-Silicon Correlation
• PPA Optimization

Preferred Skills

• Experience in both SRAM and MRAM
• Experience in advanced process technologies
• High-density / high-performance memory IP development
• Yield improvement and failure analysis
• Production ramp-up and IP qualification
• Technical leadership / team mentoring

Education

B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics Engineering or a related discipline.

Important: Candidates must have relevant SRAM/MRAM Memory Design experience. Profiles without hands-on Memory Design experience will not be considered.