Memory Layout Engineer

We are hiring skilled Memory Layout Engineers for an exciting opportunity with a leading semiconductor product company.

Candidates should have strong expertise in full custom layout design, memory blocks, and advanced technology nodes.

Key Responsibilities:

• Full custom layout implementation for high-performance arrays and memory blocks
• Layout planning, verification, and optimization for speed, power, and area
• Physical verification using DRC/LVS/DFM methodologies
• Debugging complex LVS/DRC issues using Calibre tools
• Working on advanced process nodes including 7nm/5nm/3nm technologies

Required Skills:

• Strong experience in Memory Layout Design
• Hands-on experience with Cadence Virtuoso
• Expertise in Calibre verification tools
• Understanding of datapath, bitcell arrays, wordline drivers, and control blocks
• Knowledge in advanced node layout methodologies
• Scripting knowledge in Tcl/Perl/Shell/Skill is an added advantage

Preferred Notice Period:

Immediate to 30 Days