Mid Level ASIC Design Engineer

Who you are

• 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog
• Experience in IP integration, specifically CPU IP into SoC
• Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
• Familiarity with AMBA/APB/AXI Protocol
• Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ...
• Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
• Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
• Previous experience with timing closure at high frequencies is a plus
• Interest to explore AI architectures for convolution, transformer and other kinds of workloads
• Self-starter and highly-motivated to work in a dynamic start-up environment
• B.S. (M.S. preferred) degree in Electrical or Computer engineering

What the job involves

• As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC
• This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power
• Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure
• Author/Understand micro-architecture specifications and participate in specification and test plan reviews
• Implement complex RTL designs
• Integrate CPU and other relevant IPs into the CPU sub-system
• Collaborate with the physical design team to resolve implementation and timing issues and to optimize power
• Analyze code coverage and provide feedback to the verification team to achieve coverage closure
• Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab