MTS SOC Design Verification Engineer

MTS SOC Design Verification Engineer

Company: Mettlesemi Systems and Technologies Pvt. Ltd.
Location: Bangalore
Experience: 10+ Years
Notice Period: Immediate to 30 Days

Job Description

Mettlesemi Systems and Technologies Pvt. Ltd. is looking for an experienced Senior SoC Design Verification Engineer to join our team in Bangalore. The ideal candidate should have strong expertise in SoC/Full-Chip Verification, SystemVerilog, UVM, and high-speed interface verification, particularly Ethernet, PCIe, and other HSIO protocols.

Key Responsibilities

• Develop and execute verification plans for complex SoC, subsystem, and full-chip designs.
• Develop and enhance UVM/SystemVerilog-based constrained-random verification environments.
• Create and execute complex C and SystemVerilog test cases using reusable verification libraries.
• Work closely with design teams to identify critical verification scenarios and ensure comprehensive coverage.
• Perform verification of high-speed interfaces, including Ethernet, PCIe, DDR, and other HSIO protocols.
• Work on AMBA bus protocols, including AXI, AHB, APB, and ACE.
• Perform RTL and Gate-Level Simulation (GLS) and debug complex verification issues.
• Work on functional coverage, coverage analysis, and coverage closure.
• Support low-power verification and power management flows.
• Contribute to SoC boot flow, clocking, platform bring-up, emulation, and silicon validation.
• Mentor junior engineers and contribute to the quality and timely delivery of verification activities.

Required Skills

• Strong experience in SoC Design Verification at subsystem and full-chip level.
• Strong hands-on experience with Verilog and SystemVerilog.
• Strong expertise in UVM-based verification methodology and constrained-random verification.
• Experience in Ethernet, PCIe, DDR, and High-Speed Interface/HSIO verification.
• Good understanding of AMBA protocols AXI, AHB, APB, and ACE.
• Experience with SystemVerilog Assertions (SVA).
• Experience in RTL and GLS simulations.
• Knowledge of functional coverage and coverage closure.
• Experience in Low-Power Verification and power management flows.
• Experience with SoC boot flow, clocking, platform bring-up, emulation, or silicon validation is preferred.
• Strong debugging, problem-solving, and communication skills.

Preferred Candidate

• 10+ years of relevant experience in SoC Design Verification.
• Candidates who can join immediately or within 30 days are preferred.