MTS/Senior MTS/Principal Characterization Engineer

Position Overview

We are seeking an experienced Post-Silicon Characterization Engineer to lead silicon characterization for FPGA products.

The Engineer will drive characterization projects from planning and silicon bring-up through PVT testing, data analysis, debugging, technical review, and closure. The role requires strong hands-on lab skills, technical judgment, and effective collaboration with Design, Software, Applications, and Quality teams.

Key Responsibilities

1. Develop and execute comprehensive post-silicon characterization plans across process, voltage, and temperature (PVT).

2. Lead characterization projects from initial silicon checkout through final report and product readiness.

3. Characterize and validate FPGA high-speed interfaces such as:

   1. PCIe Gen5, 25G Ethernet, LPDDR5/5x

4. Perform electrical and timing measurements such as:

   1. Eye diagram and jitter analysis
   2. BER and link-margin testing
   3. Timing and frequency margin characterization

5. Debug silicon, RTL, firmware, board, and test-setup issues.

6. Correlate bench results with simulation, design expectations, and product specifications.

7. Use statistical methods to analyze silicon variation, margin, capability, and outliers.

8. Provide clear technical conclusions, risk assessments, and recommendations to project stakeholders.

9. Work closely with Design, Product Engineering, Test, Application, Package, Board, and Quality teams to drive issue resolution.

10. Mentor junior engineers and provide technical guidance during test planning, debugging, and data review.

11. Support external laboratory, equipment vendor, board vendor, and socket vendor coordination when required.

12. Prepare and present characterization results during technical and management reviews.

Requirements

• Bachelor’s or Master’s Degree in Electrical / Electronics Engineering or related field.
• 15+ years’ experience in FPGA post-silicon validation or characterization, or high-speed interface testing.
• Experience in at least one major high-speed or memory protocol (PCIe, DDR, MIPI, Ethernet, etc.).
• Hands-on experience with lab equipment (BERT, high-bandwidth oscilloscopes, VNA, power supply, pulse generator, etc.).
• Proficiency in Python or similar scripting for automation.
• Ability to interpret schematics, datasheets, S-parameters, and simulation results.
• Strong analytical thinking and structured documentation practices.
• Experience leading validation efforts or mentoring junior engineers.
• Automotive-grade validation experience (AEC-Q100) is a plus.