NPU/AI Processor Synthesis Lead

General Summary

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.

Key Responsibilities

• Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).
• Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
• Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
• Collaborate with STA teams to resolve setup/hold violations.
• Apply physical-aware synthesis techniques to meet aggressive PPA targets.
• Implement low-power strategies using UPF/CPF flows.
• Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.
• Work closely with RTL design, DFT, and physical design teams for seamless handoff.
• Provide feedback to architecture and RTL teams for QoR improvements.
• Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.
• Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.
• Mentor junior engineers and drive best practices across synthesis and timing teams.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.