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Package and Chip thermal/stress simulation engineer

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Onsite

Package and Chip thermal/stress simulation engineer

MediaTek

Package and Chip thermal/stress simulation engineer

3 months ago

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Important information


Contract type:

Permanent

Location:

Hsinchu, North District, Hsinchu City, Taiwan

Work mode:

Onsite

Published on:

7 August 2026

What they need


  • Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation

Main Requirements and Qualifications

    1. Familiar with package thermal characterization modeling and validation flow.
    1. Familiar with package stress modeling, reliability test and its corresponding failure mode.
    1. Experience on system level modeling is a plus.

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