Package Architect - Multi-Chiplet Package

About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

Responsible for architecting and delivering advanced semiconductor packaging solutions for high-performance, high-power, and high-bandwidth products. This role owns package architecture, chiplet/die-to-die (D2D) integration, silicon-package-system co-design, signal integrity/power integrity (SI/PI), and thermal and mechanical co-optimization—from early architecture through new product introduction (NPI) and high-volume production.

Technical Skills & Expertise

• Experience in semiconductor packaging, package layout, or silicon-package co-design, with direct experience defining advanced packaging architectures for high-performance computing (HPC), AI, or networking platforms.
• Extensive experience with high-speed interfaces, including SerDes, PCIe, and die-to-die (D2D) interconnects.
• Hands-on experience with 112G–224G SerDes design, along with LPDDR and HBM memory design solutions.
• Experience defining package stack-ups, selecting materials, and developing ball-map definitions.
• Proficiency with EDA tools such as Xpedition Layout, Xpedition Substrate Integrator, ADS, Ansys, Sigrity, and related tools.
• Proven track record of successfully bringing up packages and products targeting high-power and high-bandwidth applications, from initial concept and architectural definition through final product introduction.
• Deep expertise in evaluating trade-offs across silicon floorplanning/layout, die-to-die connectivity topologies (e.g., UCIe-S and UCIe-A), and package technology selection.
• Proven experience architecting 2.5D/3D systems, chiplet implementations, and high-density substrate topologies.
• Broad knowledge across signal integrity/power integrity (SI/PI), mechanical and thermal engineering, and board/system design.
• Background in high-power solutions and multi-chiplet integration, including package- and system-level trade-offs.

What You'll Drive & Bring to the Role

• Lead the definition, trade-off analysis, and technical roadmap for advanced packaging platforms, including 2.5D/3D packaging, chiplets, interposer designs, and hybrid bonding.
• Drive cross-functional co-optimization with silicon design, signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to identify and resolve structural, electrical, and thermal bottlenecks early in the product lifecycle.
• Drive the full architecture lifecycle, from inception through high-volume product introduction, for high-power and high-bandwidth applications.
• Drive architectural decisions and co-design for high-speed interfaces, ensuring signal and power integrity across SerDes, PCIe, and die-to-die (D2D) interconnects.
• Perform multi-objective trade-off analyses across silicon layout, die-to-die connectivity options, package design, and technology choices, balancing cost, yield, manufacturability (DFM), thermal performance, electrical performance, and form factor.
• Collaborate with board and system design teams to define ball-map/pinout optimization, high-speed routing strategies, board-level reliability (BLR), and assembly rules.
• Lead technical engagements with OSATs, foundries, and substrate suppliers, evaluating new process capabilities, driving design for manufacturability (DFM), and guiding technologies from NPI through high-volume production ramp.
• Establish internal package design guidelines, technical specifications, and qualification requirements.

Required Qualifications

• M.S. or Ph.D. in Electrical Engineering/ Materials Science/ Mechanical engineering, or a related field.
• 14–18 years of work experience.

Why Join Us?

Own. Innovate. Make an Impact.

Join a talented team building next-generation compute solutions and working on cutting-edge technology. Take ownership, collaborate with exceptional engineers, grow your skills, and make an impact in a culture that values innovation, technical excellence, and teamwork.

Benefits

• Competitive Compensation aligned with industry benchmarks.
• Comprehensive Health Insurance covering employees and eligible dependents.
• Stock Options & Ownership Opportunities providing employees with an opportunity to share in the company's growth and success.