Package Layout Engineer

Advanced Package Layout Engineer

Mountain View, CA – Onsite

We’re working with an early-stage AI compute company developing a full-stack platform built around system-on-wafer architecture and advanced 3D integration. The aim is to reduce the power, latency and infrastructure costs associated with moving data across conventional AI clusters.

Advanced packaging is central to the platform, connecting multiple dies, high-bandwidth memory and high-current power delivery within a tightly integrated system.

They’re hiring an Advanced Package Layout Engineer to own multi-die 2.5D and 3D package layout from bump-map planning through tape-out release. You’ll work between the silicon and board teams, taking responsibility for the designs that substrate suppliers and assembly partners manufacture.

The role

• Own package substrate and interposer layout, including stackup definition, bump and ball maps, RDL, escape routing and manufacturing release.
• Plan high-density routing and HBM-class channels alongside power and ground structures supporting accelerator rails carrying hundreds of amps.
• Partner with physical design engineers on die floorplans and bump placement, and with PCB layout engineers on the package-to-board interface.
• Close package DRC/LVS and netlist verification against substrate supplier and OSAT design rules, negotiating rules where the design requires it.
• Work with architecture, SI/PI, thermo-mechanical and manufacturing partners to resolve trade-offs and achieve package sign-off.
• Develop and use AI-assisted tools to accelerate package layout, routing and sign-off.

Your experience

• At least eight years of package layout experience on high-performance designs, including multi-die 2.5D and 3D packages.
• Strong practical experience with advanced packaging technologies such as CoWoS, EMIB, InFO, fan-out or equivalent interposer technologies.
• Deep expertise in substrate and interposer routing, high-density escape, stackup design and via structures.
• Experience designing power and ground planes for high-current accelerator rails.
• Hands-on experience with Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer or equivalent tools.
• Practical ownership of package DRC/LVS, netlist verification and design release.

Why join?

You’ll own a critical part of how a new AI computing platform becomes working hardware. Package layout decisions will directly affect how the silicon connects, receives power and integrates with the wider system.

The role offers broad technical ownership, close collaboration with silicon and board engineers, and responsibility for the release that manufacturing partners build from.

This is an opportunity for someone who wants to solve advanced packaging problems and take a complex multi-die design through to manufacturing release.

Interested? Let’s chat!