Packaging Design Engineer

About the role

You will be part of a worldwide R&D team developing high-performance package designs for ASICs used in artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 200G and higher, RF/Microwave ADC/DAC, DDR, HBM, and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design.

Key responsibilities

• Overall design responsibility for ASIC package designs (layout/routing), including aspects of impedance matching, crosstalk, signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with experienced package engineering experts
• Package design of critical high frequency/datarate structures for SerDes, ADC/DAC, DDR, HBM, etc.
• Schedule, prioritize, and track work across multiple projects simultaneously
• General flip-chip BGA package design and engineering
• Cooperate with worldwide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

About you

• B.Eng (EE/EEE) or similar field and 5+ years' experience in flip-chip-BGA package design, including high-speed SerDes, or M.Eng (EE/EEE) or similar field and 3+ years' experience in flip-chip-BGA package design, including high-speed SerDes
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tools will also be considered
• Good organizational and task management skills to manage multiple package design projects
• B.Eng (EE/EEE) or similar field and 8+ years' experience in flip-chip-BGA package design, including high-speed SerDes preferred
• M.Eng (EE/EEE) or similar field and 6+ years' experience in flip-chip-BGA package design, including high-speed SerDes preferred
• Experience with 2.5D and 3DIC packages is highly advantageous