PCIe Hardware System Engineer

PCIe Hardware System Engineer - Taiwan

Job Description

We're in an unbelievably exciting area of tech and are fundamentally reshaping the data storage

industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team

in the industry.

This type of work, work that changes the world, is what the tech industry was founded on. So, if

you're ready to seize the endless opportunities and leave your mark, come join us.

We are seeking a highly motivated Hardware PCIe Engineer for Pure's Datastore team, based

in our new Taiwan office. Pure builds the industry's most innovative, high-performance,

energy-efficient and TCO-optimised storage solution. As part of this team, you will help

productize this differentiated storage solution for our customers, working directly with our

vendors and customers in Taiwan.

Should you accept this challenge…

Own and drive the triage, root cause, and resolution of issues raised by internal teams,

manufacturing, vendors, and customers.

PCIe Gen5 (must) and Gen6 interfaces

NVMe features

SMBus

Serve as the primary on-the-ground PCIe technical interface with our Taiwan-based

vendors and customers (JDM/ODM partners, SSD suppliers, flash controller vendors,

and enterprise customers), with on-site debug at vendor and customer facilities when

needed.

Operates as a self-motivated, self-directed engineer. Identify problems before they

escalate and drive them to closure across time zones with minimal supervision.

Ensure proper documentation and regular update to stakeholders throughout the triage

to resolution journey.

Guide the development of PCIe, NVMe, and SMBus validation test plan for early phase

chip bring-up and regression testing throughout the development cycle.

Lead failure analysis and root cause investigations to support field issues and customer

escalations.

Leverage automation and AI to improve issue triaging, utilizing company-supported tools

like Augment and Glean to facilitate agent development and harness advanced AI skills.

Provide technical leadership and mentorship to junior engineers as the Taiwan hardware

team grows.

What you'll need to bring to this role…

Over 7+ years of experience in advanced interface issue troubleshooting, root cause

analysis, and solution identification, encompassing complex system-level interactions

across host, PCIe, and CXL interfaces in enterprise server and SSD environments.

Developed and automated comprehensive validation and testing solutions.

BS in Electrical or Computer Engineering (or related field).

Proven track record in chip bring-up and product qualification.

Hands-on experience with PCIe Gen5/Gen6.

Proficient with test equipment including PCIe analyzer, Exerciser or Jammer, I2C

analyzer, and UART.

Experience with PCIe compliance testing (SIG) for SSD products.

Proficient in scripting with Python, BASH, and similar languages. Hands-on experience

in a Linux environment.

Demonstrated experience collaborating with vendors and/or customers in Taiwan (JDM/ODM, SSD/flash-controller suppliers, or enterprise customers).

Self-motivated and self-directed, with a proven ability to operate independently as the

most senior local engineer without daily oversight.

Detail-oriented, analytical, process-driven, and customer-focused.

Thrive in fast-paced, evolving business environments.

Clear and effective communicator in Mandarin and English, both verbally and in writing.

Preferred qualifications…

Firmware background. Prior hands-on FW development or FW-debug experience

(especially SSD/NVMe or PCIe FW). Strongly preferred, as this role sits at the HW/FW

boundary during triage.

MS in Electrical or Computer Engineering (or related field).

Background in collaborating with hyperscale customers.

Familiar with ARM-based firmware architecture and understanding of PCIe LTSSM.

Skilled in SSD hardware design, development and standards.

Familiar with NVMe architecture and implementation.

Knowledgeable in major bus technologies, including Ethernet, DDR, NAND, SPI, and

I²C.

Solid foundation in x86 and AMD platforms. Level: MTS-4

Location: Taiwan

Must have

PCIe protocol and trace experience (Gen5; Gen6 a strong plus)

NVMe protocol hands-on (analyzer traces, NVMe-CLI, queue/command-level debug)

LTSSM

PCIe, signal integrity knowledge and debug

System interop experience

Hands-on with Teledyne LeCroy and/or Keysight PCIe analyzers

High-speed oscilloscope and BERT experience for PCIe physical-layer debug

Proven ability to drive cross-functional debug with FW, SoC design, and BIOS teams

Python scripting

Self-motivated, self-directed

Track record working with vendors and/or customers in Taiwan

Nice to have

Firmware background (SSD/NVMe or PCIe FW)

CXL exposure

PAM4 / SerDes equalization tuning (Gen6-ready)

BIOS and Linux kernel storage stack familiarity

Customer joint qualification (JQ) experience with hyperscalers or enterprise customers

Automated regression / validation framework development (Python-based, shift-left)

SSD hardware design experience

PCI-SIG compliance experience