A
ACL Digital
PD Engineer
Skills
Python
10 months ago
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Important information
Location:
San Francisco, CA, USA
Work mode:
Onsite
Published on:
31 August 2026
What they need
- Experience : 8+
- Block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.
- Architect implementation strategies for high performance RISC-V cores, supporting complex clock/power domains and floorplans.
- Collaborate with RTL, STA, and verification teams to ensure timing and physical convergence.
- Own advanced physical design tasks including:
- EM/IR and power grid optimization for high-current blocks
- Congestion mitigation and routing-aware floorplanning
- RC-aware timing closure across corners and PVTs
- Clock tree synthesis and skew management across domains .
- Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
- Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.
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