PD PNR Engineer

Job Summary

Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams. Expected to independently own critical tiles, deliver high-quality milestones, and contribute to methodology and automation improvements.

Responsibilities

• Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff.

• Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization.

• Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets.

• Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration.

• Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges.

• Support milestone deliveries and ensure quality execution aligned with project schedules.

• Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency.

• Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing.

  Required Qualifications

• Bachelor s or Master s degree in Electrical/Electronics Engineering, VLSI, Computer Engineering, or related field.

• 7 to 10 years of experience in Physical Design or ASIC implementation.

• Strong understanding of digital design fundamentals and VLSI implementation flows.

• Hands-on experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation.

• Good understanding of STA concepts, timing optimization, and physical design signoff requirements.

• Proficiency in scripting using Tcl, Python, Perl, or Shell.

• Strong debugging, analytical, and problem-solving skills.

• Excellent communication and cross-functional collaboration abilities.

  Preferred Experience

• Experience in converging large and complex CPU, GPU, NOC, AI/ML, or networking tiles.

• Exposure to advanced technology nodes (5nm, 4nm, 3nm or below).

• Knowledge of power optimization, EMIR, CDC, RDC, and physical verification methodologies.

• Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, RedHawk, or equivalent EDA tools.

• Proven track record of independently leading critical tiles and driving milestone deliveries.

• Experience in PPA optimization, methodology development, AI-assisted PD flows, and automation initiatives.

• Ability to guide junior engineers and act as a technical lead for assigned tiles.

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