Physical Design Engineer

该职位来源于猎聘 Job Description Looking for a talented and highly self-motivated candidate that has strong background and hands-on experience in the physical design for advanced technology nodes. The candidate will work on the physical implementation of our state-of-art SoC products. Driving all aspects from RTL to GDS including timing and physical trade-offs, die size reduction and delivery of final product on schedule while meeting design goals. Responsibilities:

• Perform physical implementation of the ASIC design from netlist to GDS, including floorplanning, power grid and clock network implementation, place and route, timing closure and physical verification.
• Work with multiple teams on the SoC architecture study and timing/power/area design target.
• Working with different IP owners to ensure seamless IP integration at full chip level.
• Writing scripts for design automation flow and productivity enhancement. Job Requirement:
• Experience in ASIC Physical Design from netlist to GDSII.
• Experience in using EDA tools such as Synopsys ICC or Cadence SOC Encounter
• Hands on experience in Floorplanning, CTS, STA
• Experience in Power grid, clock tree, and low-power flow implementation methods
• Hands on experience with STA using Primetime, power analysis.
• Hands on experience with IR drop analysis, formal verification and physical verification.
• Timing closure, ECO process using PrimeTime
• Programming and scripting skills (Tcl, perl ,shell)
• DFT/DFM knowledge is a plus
• Self-motivated and able to work effectively in a start-up environment
• Ability to execute to stringent schedule & die size requirements and effective communication skills 工作职责： - 负责芯片从网表到GDS的后端物理实现，包括布局规划，时钟树生成（CTS）， 布局布线，时序优化和收敛，以及GDS的物理验证 - 和多个设计团队合作制定芯片结构，参与制定芯片性能/面积/功耗等方面的设计目标， - 与不同功能模块的设计团队合作保证功能模块的顺利集成。 - 优化后端设计自动化的流程和提高团队设计开发效率 任职要求 - 后端工作经验，微电子或者相关学科硕士以上学历 - 良好的沟通能力和团队精神，能够在精干的团队环境里高效率的发挥自己的能力。 - 熟练使用主流P&R流程工具（Synopsys、Cadence的相关P&R工具） - 具有从netlist到GDS整个流程的实际经验，包括布局规划，power gird，时钟树生成(CTS)，布局布线设计，时序收敛，IR-drop，lvs/drc。 - 具备扎实的时序分析知识与signoff的技能。 - 具备DFT/DFM相关经验的优先。 - 熟练的脚本编写技能（Tcl，perl, shell)