Physical Design Engineer

Position: Physical Designer Engineer Level: Mid- Senior

Location: West Bank-Onsite

Contract Type: Full-Time for 1-Year (Renewable) Working hours: Palestine Time Zone

Salary: Competitive Package based on Experience

No. of Vacancies : 2

Overview GGateway is seeking experienced Physical Design Engineers to join our team in supporting one of our international semiconductor clients. Engineers will work onsite from our West Bank office as part of a high-performance Physical Design team responsible for implementing complex SoCs from floorplanning through signoff. The ideal candidate has a strong ownership mindset, excellent debugging skills, and experience driving timing, power, area, and physical convergence on advanced technology nodes.

Responsibilities, Duties, and Expectations

• Own and execute block- or chip-level physical implementation using Cadence Innovus.
• Drive floorplanning, power planning, placement, CTS, routing, ECO implementation, and physical convergence.
• Achieve timing closure across MCMM scenarios while optimizing PPA (Power, Performance, Area).
• Perform STA using PrimeTime/PrimeClosure and resolve setup, hold, SI, noise, and clock-related violations.
• Analyze and resolve congestion, short/open, DRC, LVS, antenna, IR-drop, EM, and physical signoff issues using industry-standard signoff tools (Calibre, ICV, Voltus, RedHawk…etc).
• Develop TCL, Python, Perl, or Shell scripts to automate implementation, reporting, and design checks.
• Collaborate closely with different teams throughout the implementation cycle.
• Participate in design reviews, root-cause analysis, methodology improvements, and best-practice development.
• For Senior Engineers: provide technical leadership, mentor junior engineers, review implementation strategies, and drive project execution to successful tape-out.

Qualifications For Senior Candidates (5+ years of experience)

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 5+ years of industry experience in digital physical design.
• Proven experience delivering successful tape-outs for complex SoCs at advanced technology nodes (5nm and below).
• Strong expertise in floorplanning, power planning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Hands-on experience with Innovus, PrimeTime, and verification tools such as Calibre.
• Strong understanding of MCMM methodology, SI, IR-drop, EM, and low-power implementation.
• Excellent scripting skills in TCL plus Python, Perl, or Shell.
• Ability to lead technical discussions, mentor engineers, estimate schedules, and drive implementation independently.

For Mid-Level Candidates (2–5 years of experience)

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 2–5 years of industry experience in digital physical design.
• Hands-on experience with floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Hands-on experience with Innovus, PrimeTime, and verification tools such as Calibre.
• Experience with TCL scripting; Python or Perl.
• Strong analytical, debugging, communication, and teamwork skills.

Preferred (Not Required) Skills For All Levels

• Experience with advanced technology nodes (7nm/5nm/3nm).
• Knowledge of UPF/CPF low-power implementation.
• Familiarity with Verilog/SystemVerilog and DFT concepts.
• Experience with CI/CD, regression automation, and design methodology development.