Physical Design Engineer

XinPal Malaysia is part of an MNC headquartered in Singapore, specializing in delivering innovative technology solutions and supporting cutting-edge semiconductor projects. We are committed to building a high-performing team through innovation, collaboration, and continuous growth opportunities.

We are looking for a Physical Design Engineer in Bayan Lepas, Penang to support the end-to-end ASIC/SoC physical design process. The role involves floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), timing closure, physical verification (DRC/LVS), ECO implementation, and power-aware design optimization. You will collaborate with cross-functional engineering teams to ensure successful chip implementation and physical design closure for advanced semiconductor technologies.

【Job Description】

1. Execute floorplanning, placement, clock tree synthesis (CTS), and routing activities for advanced technology nodes (16nm/7nm/5nm/4nm/3nm).
2. Perform Static Timing Analysis (STA) and drive timing closure by identifying and resolving setup and hold violations.
3. Develop and manage synthesis flows, timing constraints, and implementation methodologies.
4. Conduct physical verification activities, including DRC and LVS debugging and closure using industry-standard tools.
5. Implement and optimize Engineering Change Orders (ECOs), including clock push/pull adjustments, net-delay insertion, and shorts cleanup.
6. Drive power-aware physical design implementation using low-power design techniques and methodologies.
7. Collaborate with design, verification, and integration teams to ensure successful project execution and physical design closure.
8. Work independently on synthesis, place-and-route (PnR), STA, physical design (PD), and physical verification (PV) closure for live projects.

【Requirements】

1. Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
2. Minimum 1 year of experience in ASIC/SoC Physical Design implementation, exceptional entry-level candidates are encouraged to apply.
3. Hands-on experience with Cadence Innovus is required.
4. Strong understanding of digital physical design flow, including floorplanning, placement, CTS, routing, timing closure, and physical verification.
5. Experience with Static Timing Analysis (STA), timing constraints, and synthesis methodologies.
6. Familiarity with DRC/LVS verification and debugging using Calibre or equivalent tools.
7. Proficiency in TCL scripting for automation and design flow enhancement.
8. Knowledge of low-power design techniques and power-aware implementation methodologies.
9. Experience working on advanced technology nodes is highly preferred.