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Physical Design Engineer

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Onsite

Physical Design Engineer

Cyient

Physical Design Engineer

Skills

NodePython

2 months ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

10 September 2026

What they need


Job Summary:**

CYIENT SEMICONDUCTORS PRIVATE LIMITED is seeking a highly motivated and skilled Physical Design Engineer to contribute to the full lifecycle of ASIC/SoC physical implementation, from netlist to GDSII. This role involves tackling complex design challenges in advanced technology nodes and ensuring high-performance, low-power, and area-optimized designs.

Job Responsibilities:**

* Perform all aspects of physical design, including floor planning, power planning, place and route, clock tree synthesis (CTS), timing closure (STA), signal integrity analysis, and physical verification (DRC/LVS).
* Collaborate with front-end design, DFT, and package teams to ensure successful integration and meet design specifications.
* Analyze and resolve complex timing, power, and area issues through iterative physical design methodologies.
* Develop and implement automation scripts to improve efficiency and productivity of physical design flows.
* Participate in technology node evaluation and contribute to the definition of design methodologies and best practices.
* Generate and review physical design documentation, including floor plans, timing reports, and physical verification results.
* Mentor junior engineers and contribute to knowledge sharing within the team.

Job Qualifications:**

* Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
* 3-8 years of hands-on experience in full-chip or block-level physical design for complex ASICs/SoCs.
* Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre).
* Strong understanding of static timing analysis (STA) principles and tools (e.g., Synopsys PrimeTime, Cadence Tempus).
* Solid knowledge of deep sub-micron technology issues, including signal integrity, power integrity, and DFM/DFX.
* Experience with scripting languages such as Tcl, Perl, Python, or Shell scripting.
* Familiarity with advanced technology nodes (e.g., 16nm, 10nm, 7nm, 5nm).
* Excellent problem-solving, analytical, and communication skills.
* Ability to work effectively in a team-oriented environment.

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