Physical Design Engineer

Role: Physical Design Engineer

Location: Austin, TX or San Jose, CA (Onsite)

Duration: Long term Contact

Responsibilities

• Own the full-chip physical design floorplan from architecture handoff through implementation, including die sizing, partition planning, macro and memory placement, and pin/port alignment across hierarchical block boundaries.
• Define and drive top-level chip integration strategy, including partition abutment, feedthrough planning, channel allocation, and implementation of repeating structures to ensure scalable and clean hierarchical integration.
• Lead top-level PPA (Power, Performance, Area) optimization across the chip hierarchy, balancing timing, congestion, routability, power efficiency, and area utilization.
• Architect, review, and optimize the chip-level power delivery network (PDN), collaborating closely with EM/IR and sign-off teams to ensure robust power integrity and reliability targets are met.
• Develop, maintain, and own top-level timing constraints (SDC), timing budgets, and interface requirements, partitioning constraints effectively across subsystem and block-level owners.
• Drive cross-functional reviews for floorplan, timing, power, and physical integration, identifying and resolving implementation bottlenecks early in the design cycle.
• Collaborate closely with ASIC vendors, IP providers, RTL, STA, Packaging, and block-level Physical Design teams to ensure seamless integration of IPs and successful tape-out execution.