Physical Design Engineer

Position: Physical Design Engineer

Location: Palo Alto, CA – 100% Onsite

Candidate Requirement: W2 candidates only. No C2C.

Job Summary:

• TSMC 2NP/3NP experience is required.
• Perform end-to-end physical design flow: floorplanning, power planning, placement, CTS, routing, and post-route optimization.
• Achieve timing closure across all modes and corners.
• Resolve DRC, LVS, ERC, and signoff violations.
• Experience with low-power design techniques including Multi-Vt, multi-voltage/UPF, power gating, and clock gating.
• Perform STA using PrimeTime, SI/Crosstalk, IR drop, and EM analysis.
• Experience with advanced nodes such as 7nm, 5nm, 3nm, or below.
• Collaborate with RTL, micro-architecture, DFT, test, foundry, and CAD teams.
• Debug timing, congestion, power, and variability issues.
• Drive methodology improvements and automation using scripts/flows.