Physical Design Engineer

Job highlights

• Hiring for Senior Engineer,Technical Lead,and Architect levels . Hands-on experience in handling block / chip level implementation from Netlist to GDSII . Must possess hands on experience in timing closure and physical verification closure .
• QUALIFICATION: 4-12+ YEARS EXPERIENCE
• Experience in handling lower tech nodes that include 7nm,10nm,16nm,28nm 40nm,etc

QUALIFICATION: 4-12+ YEARS EXPERIENCE
BTech/MTech in Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience

REQUIREMENTS

• Hiring for Senior Engineer, Technical Lead, and Architect levels

• Hands-on experience in handling block/chip level implementation from Netlist to GDSII

• Must possess hands on experience in timing closure and physical verification closure

• Experience in handling lower tech nodes that include 7nm, 10nm, 16nm, 28nm 40nm, etc.

• Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Innovus

• Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time

• Must possess excellent scripting skills TCL or Perl or Python

• Experience in Synthesis and Formal is a plus

RESPONSIBILITIES

• Participate at either the IP or SOC level with opportunity for change in focus as projects needs allow

• Partner with other engineers from the design team and other disciplines to define and develop ASIC physical designs. This would include physical designers from both SOC and IP

• Participate in defining flows, methods, select tools, drive continual improvement, and closure of issues

• Work with advanced process node technology