Physical Design Engineer

Position : Physical Design Engineer

Location: San Jose, CA or Austin, TX

Key Responsibilities

• Perform synthesis using Cadence Genus for large, timing-critical designs.
• Optimize PPA (Power, Performance, Area) through synthesis and early implementation.
• Develop and refine floorplans using Cadence Innovus.
• Collaborate with RTL teams on design quality, constraints, and architectural trade-offs.
• Work with external P&R teams to drive timing closure and PPA optimization.
• Identify timing bottlenecks early to improve implementation convergence.

Required Qualifications

• 5+ years of Physical Design (PD) experience.
• Experience with large-scale SoC or AI-class designs.
• Hands-on experience with advanced technology nodes (N5, N3 or below).
• Strong understanding of timing closure and synthesis-to-implementation correlation.
• Proficiency in Cadence Genus and Innovus.
• Ability to collaborate across RTL, architecture, PD, and external implementation teams.